rev.1.2 rev.1.2 description the SRM2AV413LLBT 8 is a 262,144words x 16-bit asynchronous, random access memory on a monolithic cmos chip. its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. the asynchronous and static nature of the memory requires no external clock and no refreshing circuit. it is possible to control the data width by the data byte control. 3-state output allows easy expansion of memory capacity. the temperature range of the SRM2AV413LLBT 8 is from ?0 to 85 c, and it is suitable for the industrial products. features fast access time ........................ 85ns (2.4v) low supply current ..................... ll version completely static ........................ no clock required supply voltage ............................ 2.4v to 3.3v 3-state output with wired-or capability non-volatile storage with back-up batteries package ..................................... SRM2AV413LLBT tfbga-48 pin (tape csp) block diagram i/o buffer 16 i/o1 i/o16 cs1 oe we lb ub lb , ub oe , we control logic cs1,cs2 control logic 10 8 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 address buffer memory cell array 1024 x 256 x 16 column gate 1024 256 256x16 x decoder y decoder cs2 4m-bit static ram pf1061-05 SRM2AV413LLBT 8 super low voltage operation and low current consumption access time 85ns (2.4v) 262,144 words x 16-bit asynchronous wide temperature range super low voltage operation products
rev.1.2 2 SRM2AV413LLBT 8 pin configuration a b c d e f g h 2 13456 lb oe a0 a3 a5 a17 nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 cs1 i/o2 i/o4 i/o5 i/o6 we a11 cs2 nc nc i/o1 i/o3 v dd v ss i/o7 i/o8 ub i/o9 i/o10 i/o11 i/o12 i/o12 i/o13 i/o14 nc a8 i/o15 i/o16 v ss v dd tfbga-48 pin top view (looking through part) SRM2AV413LLBT pin description a0 to a17 we oe cs1 lb ub i/o1 to 16 v dd v ss nc address input write enable output enable chip select1 chip select2 lower byte enable upper byte enable data i/o power supply (2.4v to 3.3v) power supply (0v) no connection cs2
rev.1.2 3 SRM2AV413LLBT 8 absolute maximum ratings supply voltage input voltage input/output voltage power dissipation operating temperature storage temperature soldering temperature and time parameter v dd v i v i/o p d t opr t stg t sol symbol ratings unit 0.5 to 4.0 0.5 * to v dd + 0.3 0.5 * to v dd + 0.3 0.5 40 to 85 65 to 150 260 c, 10s (at lead) (v ss =0v) * v i ,v i/o (min.) = 2.0v (when pulse width is less than 50ns) v v v w c c dc recommended operating conditions (ta = 40 to 85 c) parameter supply voltage input voltege symbol v dd v ss v ih v il v v v v * if pulse width is less than 50ns it is 2.0v min. 2.4 0.0 0.75v dd 0.3 * typ. 3.0 0.0 max. 3.3 0.0 v dd +0.3 0.3 min. 2.7 0.0 2.0 0.3 * typ. 3.0 0.0 max. 3.3 0.0 v dd +0.3 0.6 unit v dd = 2.4 to 3.3v v dd = 2.7 to 3.3v electrical characteristics dc electrical characteristics parameter symbol conditions unit input leakage current standby supply current average operating current operating supply current high level output voltage i li i lo v oh i oh low level output voltage v ol i dds i dds1 i dda i dda1 i ddo i ol a (v ss =0v, ta = 40 to 85 c) v dd = 2.4 to 3.3v v i = 0 to v dd lb and ub = v ih or cs1 = v ih or cs2 = v il or we=v il or oe = v ih , v i/o = 0 to v dd cs1 = v ih or cs2= v il output leakage current 1.0 min. typ. *1 max. 1.0 a 1.0 1.0 ma a ma 25 35 ma 4.0 6.0 ma 4.0 6.0 v v 2.0 v dd 0.2 0.4 0.2 *1 : typical values are measured at ta = 25 c and v dd = 3.0v v i = v il or v ih i i/o = 0ma, t cyc = min. v i = v il or v ih i i/o = 0ma, t cyc = 1 s v i = v il or v ih i i/o = 0ma 0.5ma 100 a 1.0ma 100 a 0.5 ta 25 c, v dd 3.0v cs1 = cs2 v dd 0.2v or cs2 0.2v 1.0 15 1.0 terminal capacitance (ta = 25 c, f = 1mhz) parameter symbol unit conditions address capacitance input capacitance i/o capacitance c add c i c i/o v add = 0v v i = 0v v i/o = 0v max. min. typ. note : this parameter is made by the inspection data of sample, not of all products 8 8 10 pf pf pf
rev.1.2 4 SRM2AV413LLBT 8 1ttl i/o c l *1 test conditions 1. input pulse level : 0.3v to 0.8v dd (2.4vto 3.3v) 2. t r = t f = 5ns 3. input and output timing reference levels :1/2v dd (2.4v to 3.3v) 4. output load : c l =50pf (includes jig capacitance) *2 test conditions 1. input pulse level : 0.3v to 0.8v dd (2.4v to 3.3v) 2. t r = t f = 5ns 3. input timing reference levels :1/2v dd (2.4v to 3.3v) 4. output timing reference levels : 200mv (the level changed from stable output voltage level) 5. output load :c l = 5pf (includes jig capacitance) ac electrical characteristics ? read cycle unit SRM2AV413LLBT 8 2.4 to 3.3v min. 85 5 0 0 5 max. 85 85 85 45 45 30 30 30 30 parameter symbol test conditions (v ss = 0v, ta = 40 to 85 c) read cycle time address access time cs1 access time cs2 access time oe access time lb, ub access time cs1 output set time cs2 output set time cs1 output floating cs2 output floating lb, ub output set time lb, ub output floating oe output set time oe output floating output hold time t rc t acc t acs1 t acs2 t oe t ab t clz1 t clz2 t chz1 t chz2 t blz t bhz t olz t ohz t oh 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 ns ns ns ns ns ns ns ns ns ns ns ns 5 ns ns ns ? write cycle unit SRM2AV413LLBT 8 2.4 to 3.3v 85 70 70 70 0 60 70 0 35 0 5 parameter symbol test conditions (v ss = 0v, ta = 40 to 85 c) write cycle time chip select time (cs1) chip select time (cs2) address enable time address setup time write pulse width lb, ub select time address hold time data setup time data hold time we output floating we output set time t wc t cw1 t cw2 t aw t as t wp t bw t wr t dw t dh t whz t ow 1 1 1 1 1 1 1 1 1 1 2 2 ns ns ns ns ns ns ns ns ns ns ns min. max. 35 ns 1ttl i/o c l
rev.1.2 5 SRM2AV413LLBT 8 timing chart t chz2 cs1 read cycle *1 a0 to 17 lb, ub oe i/o1 to 16 (dout) t rc t acc t blz t oe t ohz t olz write cycle 1 (cs1 control) *2, *3 t aw t dw t wr t as t dh write cycle 3 (we control) *3 write cycle 4 (ub, lb control) a0 to 17 cs1 lb, ub we i/o1 to 16 (dout) (din) t oh high-z t bw t chz1 t clz1 cs2 cs2 t wc t cw1 t wp t dw t wr t as t dh a0 to 17 cs1 lb, ub we i/o1 to 16 (dout) (din) high-z cs2 t wc t cw1 t wp t dw t bw t wr t as t whz t ow t dh a0 to 17 cs1 lb, ub we i/o1 to 16 (dout) (din) t cw2 write cycle 2 (cs2 control) *2, *3 t aw t dw t wr t as t dh a0 to 17 cs1 lb, ub we i/o1 to 16 (dout) (din) high-z t bw cs2 *3 cs2 t cw2 t wp t cw2 t bw t cw1 t wc t acs1 t wp t ab t acs2 t clz2 t cw2 t wc t cw1 t bhz note : * 1 during read cycle time, w e is to be "high" level. * 2 in write cycle time that is controlled by c s 1 or cs2, output buffer is to be "hi-z" state even if o e is "low" level. * 3 when output buffer is in output state, be careful that do not input the opposite signals to the output data. data retention characteristic with low voltage power supply parameter symbol conditions min. typ.* max. unit data retention supply voltage data retention curren data hold time operation recovery time v ddr i ddr t cdr t r v a ns ms (v ss = 0v, ta = 40 to 85 c) v ddr = 2.5v cs1 = cs2 v dd 0.2v or cs2 0.2v * : reference data at ta=25 c 1.2 0 5 0.4 3.3 13
rev.1.2 6 SRM2AV413LLBT 8 functions truth table cs1 x l l l l l l l l x x h l h l l h l lb x x h h l l h l l ub x h x x x x l l l oe x x h x l l l h h h we i/o1 to 8 i dd mode i dds , i dds1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 high-z high-z data in high-z data in dataout high-z data out i/o9 to 16 high-z high-z high-z data in data in high-z dataout data out not selected output disable lower byte write upper byte write all byte write lower byte read upper byte read all byte read x : high or low cs2 x l h h h h h h h h h xx x high-z high-z high-z high-z not selected output disable i dds , i dds1 reading data it is possible to control the data width by l b and u b pins. (1) reading data from lower byte data is able to be read when the address is set while holding c s 1 ="low",cs2 = "high", o e = "low", l l b ="low", and w e = "high". (2) reading data from upper byte data is able to be read when the address is set while holding c s 1 = "low",cs2 = "high", o e = "low", u b = "low", and w e ="high". (3) reading data from both bytes data is able to be read when the address is set while holding c s 1 = "low",cs2= "high", o e ="low", u b ="low", l b = "low", and w e = "high". since i/o pins are in "hi-z" state when o e = "high", the data bus line can be used for any other objective, then access time apparently is able to be cut down. writing data (1) writing data into lower byte there are the following four ways of writing data into memory. i) hold cs2 = "high", w e = "low", u b = "high", and l b = "low", set address and give "low" pulse to c s 1 . ii) hold c s 1 = "low",w e = "low",u b ="high", and l b = "low",set address and give "high" pulse to cs2. iii) hold c s 1 = "low",cs2 = "high",u b ="high", and l b = "low",set address and give "low" pulse to w e ix) hold c s 1 = "low",cs2 = "high",w e ="low",and u b = "high",set address and give "low" pulse to l b . anyway, data on i/o pins are latched up into the memory cell during c s 1 ="low",cs2 = "high",w e and l b ="low". data retention timing (cs1 control) v dd cs1 t cdr t r v ddr 1.2v cs1 v dd 0.2v 2.4v 2.4v data hold time v il v il 0.8xv dd 0.8xv dd data retention timing (cs2 control) v dd cs2 t cdr t r v ddr 1.2v cs2 0.2v 2.4v 2.4v data hold time 0.3 0.3 v ih v ih
rev.1.2 7 SRM2AV413LLBT 8 (2) writing data into upper byte there are the following four ways of writing data into the memory. i) hold cs2 ="high",w e ="low",l b ="high",and u b ="low",set address and give "low" pulse to c s 1 . ii) hold c s 1 ="low",w e ="low",l b ="high",and u b ="low",set address and give "high" pulse to cs2. iii) hold c s 1 ="low",cs2 ="high",l b ="high",and u b ="low",set address and give "low" pulse to w e . ix) hold c s 1 ="low",cs2 ="high",w e ="low",and l b ="high",set address and give "low" pulse to u b . anyway, data on i/o pins are latched up into the memory cell during c s 1 ="low",cs2 = "high",w e and u b ="low". (3)writing data into both bytes there are the following four ways of writing data into the memory. i) hold cs2 = "high", w e = "low", l b and u b = "low", set address and give "low" pulse to c s 1 . ii) hold c s 1 = "low", w e = "low", l b and u b = "low", set address and give "high" pulse to cs2. iii) hold c s 1 = "low", cs2 = "high", l b and u b = "low", set address and give "low" pulse to w e . ix) hold c s 1 = "low", cs2 = "high", w e = "low", set address and give "low" pulse to l b and u b . anyway, data on i/opins are latched up into the memory cell during c s 1 = "low" , cs2 ="high" , w e = "low", u b and l b = "low". as data i/o pins are in "hi-z" when c s 1 = "high", cs2 = "low", o e = "high", or l b and u b ="high", the contention on the data bus can be avoided. but while i/o pins are in the output state, the data that is opposite to the output data should not be given. standby mode when c s 1 is "high" or cs2 is "low" the chip is in the standby mode (only retaining data operation). in this case data i/o pins are hi-z, and all inputs of addresses, w e , o e , u b , l b , and data are inhibited. when c s 1 = cs2 v dd - 0.2v or cs2 0.2v, there is almost no current flow except through the high resistance parts of the memory. data retention at low voltage in case of the data retention in the stadby mode, the power supply can be gone down till the specified voltage. but it is impossible to write or read in this mode.
rev.1.2 8 SRM2AV413LLBT 8 unit : mm package dimensions tfbga-48 pin 123 456 h g f e d c b a 6 5 4 3 2 1 a b c d e f g h bottom view side view top view sram die base tape index 0.75 typ. 1.0 max. 0.75 typ. 8.0 0.2 0.2 10.0 0.2 0.35 0.05 +0.1 0.05
rev.1.2 9 SRM2AV413LLBT 8 characteristics curves / p s n b m j [ f e u " $ $ u " $ 4 ? 5 b u " $ 4 / p s n b m j [ f e u " $ $ u " $ 4 ? $ - u " $ 4 / p s n b m j [ f e / p s n b m j [ f e * % % 3 ? 5 b u " $ $ u " $ 4 ? 7 % % u " $ 4 5 b $ $ - q ' 7 % % 7 5 b1 $ 5 b1 $ 5 b1 $ 7 % % 1 / p s n b m j [ f e * % % " ? 5 b 3 & " % 8 3 * 5 & 7 % % 1 7 3 & " %
8 3 * 5 & / p s n b m j [ f e * % % 4 ? 5 b 7 % % 1 7 / p s n m j [ f e * % % 4 ? 7 % % 7 % % 7 5 b1 $ / p s n b m j [ f e * 0 ) ? 7 0 ) / p s n b m j [ f e * 0 - ? 7 0 - 7 0 ) 7 7 0 - 7 5 b1 $ 7 % % 1 7 / p s n b m j [ f e * % % " ? ' s f r v f o d z ' s f r v f o d z . ) [ 5 b1 $ 7 % % 1 7 3 & " % 8 3 * 5 & / p s n b m j [ f e * % % " ? 7 % % 7 % % 7 3 & " % 8 3 * 5 & 5 b1 $ 3 & " %
8 3 * 5 & 5 b $ 5 b $ 7 % % 1 7 5 b1 $ 5 b1 $ 7 % % 1 7
SRM2AV413LLBT 8 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ epson electronic devices website rev.1.2 first issue july 1999 s , printed june 2000 in japan t
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